Imec Delivers Silicon Interposer Baseline Flow
Imec's NanoIC pilot line has completed baseline flows for its silicon interposer platform ahead of a planned design kit release.
Updated on Nov. 11, 2026 in Semiconductors
Imec has delivered the baseline flows for the silicon interposer platform being developed within its NanoIC pilot line. The baseline serves as the technical basis for a dedicated silicon interposer process design kit (PDK).
Why it matters
Chiplet architectures combine multiple specialized dies in one package to meet rising performance demands of advanced AI compute. Silicon interposers provide the dense routing layer that links compute chiplets and high-bandwidth memory.
The platform supports microbump pitches down to 20 µm and includes through-silicon vias and multiple metal routing layers. It is one of three advanced interconnect technologies under development at NanoIC, which also includes fine-pitch RDL interposers and die-to-wafer hybrid bonding.
The players
Imec
Imec is a Belgium-based independent research and innovation hub in nanoelectronics and digital technologies that runs the NanoIC pilot line for advanced semiconductor development.
The details
The silicon interposer platform is being developed within Imec's NanoIC pilot line and captures its architecture, manufacturing flow and key design characteristics in a technical reference. The forthcoming PDK will use industry-standard EDA environments from Cadence and Synopsys, allowing universities, start-ups and fabless companies to explore the technology virtually.
Timeline
Early 2027: Silicon interposer PDK scheduled for release.
The Tech Race
Silicon interposers are central to chiplet-based packaging, which has become the dominant route for combining AI compute dies with high-bandwidth memory. Imec's baseline flow positions a European research pilot line to offer a comparable reference platform for designers outside the largest foundry ecosystems.
Designers at universities, start-ups and fabless companies will be able to virtually test silicon interposer designs once the PDK is released. The release gives smaller teams a route to explore advanced packaging without first building physical prototypes.
The takeaway
Silicon interposers and chiplet packaging are becoming central to how advanced AI hardware is built, so tracking PDK releases offers an early view of which designs will be accessible beyond large chipmakers.
What happens next
The silicon interposer PDK is scheduled for release in early 2027, which will open virtual exploration to universities, start-ups and fabless companies.
Further reading
Explore more on Semiconductors as advanced packaging reshapes chip design.
