Cadence PCIe 6.0 IP Passed Compliance Testing
The Cadence subsystem officially joined the PCI-SIG Integrators List in July 2026.
Updated on Sept. 28, 2026 in Semiconductors
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Cadence Design Systems completed first-pass compliance testing for its PCIe 6.0 PHY and controller IP in late July 2026. The x8 subsystem successfully met all official testing requirements at a data rate of 64 GT/s.
Why it matters
Compliance certification ensures that new high-speed interface components are interoperable within the broader computing ecosystem. Passing these rigorous standards allows the technology to be reliably integrated into future high-performance hardware designs.
The Cadence PCIe 6.0 x8 subsystem passed all official tests using the TSMC N3 process. This verification was confirmed at a data rate of 64 GT/s during the first official round of compliance workshops.
The players
Cadence Design Systems
This company is a leading provider of electronic design automation software, semiconductor intellectual property, and system design services.
PCI-SIG
This industry consortium is responsible for developing, maintaining, and managing the Peripheral Component Interconnect Special Interest Group specifications.
TSMC
This organization is a major multinational semiconductor contract manufacturing and design company.
The details
The Cadence IP subsystem was rigorously vetted at a PCI-SIG compliance workshop to ensure it met the latest industry standards for interconnect technology. By earning a spot on the PCI-SIG Integrators List, the design confirms its technical readiness for manufacturers.
Timeline
The compliance testing was completed in late July 2026.
The Tech Race
This development follows the established technical standard set by the PCI-SIG for the industry's next-generation interconnect infrastructure. It reflects the ongoing transition to the PCI Express 6.0 specification, which sets a new bar for data transfer efficiency.
This milestone speeds up the arrival of high-performance hardware, such as advanced data center servers and high-speed storage devices. Developers can now utilize this certified IP to build more efficient, faster systems with confidence in long-term interoperability.
The takeaway
Achieving early compliance with new industry standards reduces technical risk for manufacturers planning their next generation of hardware. Adopting certified IP is essential for maintaining seamless compatibility in an increasingly complex computing market.
Further reading
For more on the latest developments in chip architecture, see Semiconductors.
Source note: This article includes information reported by Design-reuse.
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