Credo Technology Toucan Retimer Earned PCIe 6.x Compliance
The company’s 7 nm device gained official certification for high-speed data transmission in August 2026.
Updated on Sept. 22, 2026 in Semiconductors
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Credo Technology received PCI-SIG 6.x compliance for its Toucan retimer on August 31, 2026. The device is now listed on the official PCI-SIG Integrators List for 16-lane operations.
Why it matters
This certification allows the retimer to be utilized in dense GPU clusters and AI accelerator platforms where signal integrity challenges require robust compensation. Its support for CXL 3.x further enables advanced processors to effectively tap into shared memory pools.
The Toucan retimer features a 7 nm process node, 11 W power consumption for x16 operations, and less than 7 ns of latency. It supports 16 lanes at 64.0 GT/s and maintains signal integrity in environments where insertion loss reaches 36 to 40 dB.
The players
Credo Technology
This semiconductor company specializes in high-speed, mixed-signal integrated circuits for the data infrastructure market.
PCI-SIG
The Peripheral Component Interconnect Special Interest Group is the industry consortium responsible for defining and maintaining PCI specifications.
The details
Designed to sit between two endpoints on a PCIe bus, the retimer restores electrical signals to maintain data integrity across demanding hardware configurations. The hardware successfully concluded testing at a PCI-SIG Compliance Workshop on July 31, 2026, paving the way for its formal 6.x certification.
Timeline
February 2026: The device passed PCIe 5.0 compliance at 32.0 GT/s.
July 31, 2026: Compliance testing concluded at a PCI-SIG workshop.
August 31, 2026: The PCI-SIG formalized the 6.x certification.
The Tech Race
The Toucan retimer is positioned to serve as a foundational component that aligns with the future trajectory of the PCIe 7.0 roadmap. This development highlights the ongoing arms race to scale interconnect speeds in line with the massive bandwidth requirements of modern AI clusters.
Data center operators can now integrate this hardware to maintain high-speed connections across massive GPU arrays. Users may benefit from improved efficiency and reduced memory access latency in high-performance computing environments.
The takeaway
The certification of 64.0 GT/s retimers is a critical step in enabling the next generation of AI and machine learning infrastructure. System architects should note these capabilities when designing hardware for environments that demand low-latency memory access.
Further reading
For more information on the industry standards enabling high-speed connectivity, visit Semiconductors.
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