Researchers Built Sub-5nm MoS2 Transistors

A multi-university team developed a CMOS-compatible process for nanoscale transistors on 4-inch wafers.

Updated on Sept. 22, 2026 in Semiconductors

Isometric editorial illustration of a single silicon wafer disk with intricate geometric patterns, representing semiconductor manufacturing technology. — A research team from four major U.S. universities has successfully developed a CMOS-compatible process to integrate MoS2 transistors at a 4-inch wafer scale. AI Illustration. Upload story photo >

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Researchers from Carnegie Mellon, the University of Florida, MIT, and Texas A&M have created MoS2 transistors with channel lengths shorter than 5 nanometers. This breakthrough demonstrates a CMOS-compatible, 4-inch wafer-scale integration process.

Why it matters

The successful integration of these materials into standard fabrication workflows is essential for scaling semiconductor performance beyond current silicon limits. This development paves the way for denser, more efficient microchip architectures.

The newly developed MoS2 transistors feature a subthreshold swing of 88 millivolts per decade and an on/off ratio exceeding 10. These devices were fabricated using a photolithography-based process designed to meet CMOS compatibility standards.

The players

Carnegie Mellon University

This private research university in Pittsburgh, Pennsylvania, is globally recognized for its contributions to computer science and engineering research.

University of Florida

This public land-grant research university in Gainesville maintains a prominent focus on semiconductor and materials science initiatives.

Massachusetts Institute of Technology

Based in Cambridge, Massachusetts, this institution is a world-leading center for technological and scientific innovation.

Texas A&M University

This public research university in College Station is a significant hub for engineering development and semiconductor research in the United States.

The details

The research team utilized a photolithography-based process to achieve high-precision fabrication of these monolayer transistors. By successfully integrating this technology at a 4-inch wafer scale, the team validated the potential for using these materials in existing industrial manufacturing environments.

The research paper was published in Nature Communications in September 2026.

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The Tech Race

This development marks a critical shift in the evolution of materials science, moving MoS2-based devices from theoretical lab models to practical wafer-scale production. It represents a direct challenge to the physical scaling limitations currently faced by traditional silicon-based transistors.

For consumers and developers, this research suggests a potential pathway toward significantly faster, more energy-efficient portable electronics and computing devices in the future. While currently experimental, the process compatibility implies that these chips could one day reach mass production without requiring entirely new infrastructure.

The takeaway

This breakthrough demonstrates that complex 2D materials can be integrated into the rigid requirements of existing chip-making standards. Future progress will focus on testing these transistors in more complex circuit environments to determine if they can effectively replace silicon in commercial applications.