Orthogone Released Low-Latency FPGA IP Portfolio
The new portfolio offers networking and data-movement cores optimized for AMD UltraScale+ and Versal platforms.
Updated on Oct. 7, 2026 in Semiconductors
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Orthogone has launched an ultra-low-latency FPGA IP portfolio designed to accelerate data processing on AMD adaptive platforms. The suite provides production-ready networking and data-movement cores intended for high-performance computing environments.
Why it matters
By offloading network processing from the host CPU to FPGA logic, this design provides the determinism, reliability, and low jitter required for critical aerospace, defense, and quantum computing applications.
The portfolio features support for Ethernet line rates of 1G, 10G, 25G, 40G, and 100G. The integrated hardware includes TCP/IP and UDP/IP offload engines along with a PCIe circular-buffer DMA controller that supports Gen3 and Gen4 interfaces.
The players
Orthogone
Orthogone is a technology company that provides design services and intellectual property for FPGA-based hardware solutions.
AMD
AMD is a global semiconductor company that produces adaptive computing platforms, including the UltraScale+ and Versal product lines.
The details
The IP cores perform packet processing and networking at sub-microsecond latency thresholds, ensuring high-speed data movement. The portfolio includes optional Reed-Solomon FEC and is specifically engineered to support AMD UltraScale+ and Versal adaptive platforms.
Timeline
October 7, 2026: Orthogone announced the availability of the portfolio.
The Tech Race
This release reflects the broader industry move toward hardware-based acceleration to handle increasing throughput demands. By targeting specialized fields like quantum computing, Orthogone positions itself to capture market share in high-stakes, low-latency infrastructure.
Developers and engineers working on aerospace or defense systems can now reduce latency by offloading network traffic directly to FPGA logic. This improvement simplifies the management of high-speed data movement, potentially streamlining the development cycle for mission-critical hardware.
The takeaway
The move toward FPGA-based offloading highlights the critical role of custom silicon in managing high-volume data streams. Professionals should evaluate their current CPU bottlenecks to determine if shifting network tasks to hardware can improve their system latency.
Further reading
Explore the latest developments in chip architecture and hardware design in our Semiconductors section.
Source note: This article includes information reported by EDN.
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