Sofics Released New Specialty I/O Topologies
The firm introduced interface solutions compatible with advanced TSMC FinFET and Nanosheet semiconductor technologies.
Updated on Sept. 25, 2026 in Semiconductors
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Sofics has launched new specialty I/O topologies designed to integrate with TSMC FinFET and Nanosheet processes, including N4C and N2P technologies. These solutions enable 1.8V and 3.3V interface capabilities for modern chip designs.
Why it matters
These tools allow advanced, low-voltage semiconductor chips to communicate effectively with sensors and legacy components that require higher voltage levels. By integrating ESD protection and voltage regulation, designers can simplify their hardware interfaces.
The new solutions support 1.8V and 3.3V interfaces on TSMC N4C and N2P technologies. The 4nm 3.3V GPIO design utilizes integrated voltage regulators and ESD protection to bridge core supplies.
The players
Sofics
Headquartered in Aalter, Belgium, this company specializes in semiconductor intellectual property for integrated circuits.
TSMC
Taiwan Semiconductor Manufacturing Company is the world's largest dedicated independent semiconductor foundry.
The details
The I/O architecture provides engineers the ability to tune drive strength, slew rate, and power consumption for their specific applications. These IP blocks are currently available for licensing to developers building on TSMC platforms.
Timeline
Sofics joined the TSMC Open Innovation Platform IP Alliance in 2010.
The specialty I/O topologies were announced on September 25, 2026.
The Tech Race
This development aligns with the ongoing integration of specialty IP within the TSMC Open Innovation Platform IP Alliance. As foundries move to smaller nodes like 4nm, maintaining compatibility with legacy high-voltage components remains a critical competitive requirement.
Developers using these new IP blocks can reduce the complexity of their hardware designs by eliminating external voltage components. This streamlining facilitates faster development cycles for devices that must bridge modern processing power with diverse legacy hardware.
The takeaway
The ability to integrate higher voltage interfaces directly onto advanced 4nm chips reduces the footprint required for peripheral communication. Engineers should evaluate these licensed IP blocks to streamline board-level designs and minimize component counts.
Further reading
Learn more about the latest developments in Semiconductors.
Source note: This article includes information reported by Design-reuse.
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