Arteris Has Released FlexGen Multi-Die Product
The new network-on-chip technology aims to optimize chiplet integration and reduce system resource requirements.
Updated on Sept. 22, 2026 in Semiconductors
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Arteris has introduced its FlexGen Multi-Die network-on-chip IP, a solution designed to support bidirectional transactions across complex chiplet architectures. The product is intended to enhance connectivity in non-coherent AI and high-performance computing systems.
Why it matters
Multi-die chiplet integration currently faces significant bottlenecks regarding I/O utilization and physical footprint constraints. This technology addresses those challenges by streamlining data flow across physical die boundaries.
The FlexGen Multi-Die technology supports bidirectional transactions over a single UCIe PHY and utilizes virtual channel links. These features enable an expected reduction in PHY area, power, and I/O requirements by up to 50%.
The players
Arteris
Arteris is a leading provider of network-on-chip intellectual property that accelerates the development of complex semiconductor systems.
Magillem
Magillem is an automation technology firm that provides software solutions for electronic system-level design and integration.
Cycuity
Cycuity is a hardware security company that specializes in verifying the integrity of semiconductor designs and systems.
The details
The product extends network-on-chip IP capabilities across die-to-die links while maintaining bandwidth and quality of service. It integrates with Magillem automation tools and Cycuity hardware security systems to support advanced non-coherent architectures.
Timeline
Arteris released the FlexGen Multi-Die product on September 21, 2026.
The Tech Race
As the semiconductor industry pivots toward heterogeneous chiplet architectures, the ability to manage interconnect efficiency has become a critical competitive differentiator. This product positions Arteris at the forefront of the movement to optimize data transport across the industry-standard Universal Chiplet Interconnect Express (UCIe) physical layer.
Engineers and chip architects can utilize this IP to simplify the design process for high-performance computing components. The resulting power and area savings allow for more efficient hardware development in future consumer AI devices.
The takeaway
Advancements in chiplet connectivity are essential as demand grows for more powerful and energy-efficient AI hardware. Streamlining the communication between disparate dies on a single package remains a primary challenge for next-generation system design.
Further reading
For more on evolving interconnect solutions, visit the Semiconductors section.
Source note: This article includes information reported by eeNews Europe.
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