Groq to Integrate 3D Stacked DRAM Into Next-Gen Chips

The company plans to transition from SRAM to vertical DRAM stacking to improve memory capacity for AI models.

Updated on Oct. 21, 2026 in Semiconductors

Isometric editorial illustration showing a stack of thin, square silicon plates, representing high-density memory storage for AI hardware. — Groq plans to implement 3D stacked DRAM technology in its next-generation chips to boost memory capacity for complex AI models. AI Illustration. Upload story photo >

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Do you believe larger storage capacity is more critical for AI development than faster processing speeds?

Groq intends to utilize 3D stacked DRAM technology in its upcoming generation of chips. The move aims to address memory limitations as modern AI models continue to grow in complexity.

Why it matters

While SRAM provides high speed, DRAM offers significantly larger memory capacities necessary for training and running massive AI models. This transition suggests a strategic shift toward prioritizing storage density over peak bandwidth speeds.

Current Groq LPX racks contain 256 LPU chips that deliver 640 TB/s scale-up bandwidth and 1.20 PFLOPs of FP8 compute per chip. The system relies on 500 MB of SRAM per LPU, while current racks provide 128 GB of total SRAM capacity.

The players

Groq

Groq is an NVIDIA-acquired firm that specializes in developing high-performance hardware for artificial intelligence processing.

The details

Groq plans to implement Through-Silicon-Vias to connect multiple DRAM layers vertically within its hardware. This configuration will allow the chips to accommodate more data, trading off some of the extreme bandwidth speeds currently provided by SRAM.

August 2026: Groq LPX racks entered full production.
October 21, 2026: The shift to 3D stacked DRAM is announced.

The Tech Race

The adoption of Through-Silicon-Vias marks a pivotal advancement in semiconductor architecture that contrasts with traditional planar memory integration. This move follows a pattern set by high-end memory manufacturers looking to solve the memory wall problem in AI acceleration.

Users and developers should anticipate future hardware capable of running larger AI models more efficiently. The change could eventually lead to improved performance in local AI applications as memory density becomes less of a bottleneck.

The takeaway

The move to 3D stacked memory represents a critical adjustment in chip design for the AI era. Developers should prepare for hardware that prioritizes massive data storage to handle increasingly complex neural networks.