NVIDIA Will Reportedly Use Intel Packaging in 2028

NVIDIA may adopt Intel's Foveros 3D stacking technology by the second half of 2028.

Updated on Oct. 9, 2026 in Semiconductors

NVIDIA Will Reportedly Use Intel Packaging in 2028

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Analyst Jeff Pu reports that NVIDIA might incorporate Intel Foveros packaging technology into its hardware designs starting in the second half of 2028. This potential partnership follows earlier reports linking NVIDIA to Intel's 14A manufacturing technology.

Why it matters

A shift toward Intel's packaging solutions could relieve critical manufacturing pressure currently placed on TSMC's production capacity. Diversifying suppliers in this way is a key strategy for maintaining the chip supply chain.

Intel Foveros technology utilizes 3D stacking of computing tiles on a base die, effectively reducing the horizontal footprint of semiconductor packages. This differs from Intel's EMIB and EMIB-T technologies, which rely on horizontal chipset placement.

The players

NVIDIA

NVIDIA is a prominent technology company that specializes in the design of graphics processing units and artificial intelligence hardware.

Intel

Intel is a multinational corporation and one of the world's largest semiconductor chip manufacturers.

Jeff Pu

Jeff Pu is a GF Securities analyst who tracks developments in the global semiconductor manufacturing sector.

Google

Google is a major technology company that has reportedly utilized Intel EMIB-T technology for its packaging requirements.

The details

Intel Foveros involves stacking computing tiles vertically on a base die, an advancement from the horizontal placement used in Intel's EMIB-T technology. Google has already utilized Intel's packaging requirements, and NVIDIA may now leverage these tools to scale production.

January 2026: Reports surfaced regarding NVIDIA potentially using Intel 14A technology.
H2 2028: Intel 14A production starts and potential NVIDIA Foveros usage begins.

The Tech Race

The adoption of advanced packaging represents a significant evolution in semiconductor design, moving away from legacy horizontal configurations toward sophisticated 3D stacking. This transition reflects a broader industry arms race to overcome physical size constraints in high-performance computing.

For users and developers, this partnership could eventually stabilize the availability of high-performance hardware by easing manufacturing bottlenecks. Greater supply chain efficiency helps keep pace with the rapidly growing demand for advanced AI and computing power.

The takeaway

The move suggests a long-term shift toward a more collaborative semiconductor ecosystem where giants share manufacturing and packaging expertise. This integration helps the industry push beyond the current limits of silicon density and production capacity.